A wide class of electrically-programmable non-volatile semiconductor memories have memory cells exploiting as storage elements MOS transistors having a charge retention element such as a polysilicon floating gate or a nitride layer, which can be charged by e.g. injection or tunneling of electric charges (electrons), typically from the MOS transistor channel or drain region.
The amount of charge in the charge retention element affects the MOS transistor threshold voltage; this mechanism is exploited for storing information in the memory cell.
The information stored in a memory cell can be retrieved by determining the MOS transistor threshold voltage, for example by biasing the MOS transistor in a predetermined condition and sensing the current flowing therethrough.
Programming one such memory cell involves applying to the MOS transistor suitable programming potentials, in particular to the control gate and the drain electrodes thereof.
In general, the programming potentials are relatively high compared to the electric potentials (read potentials) that are applied to the transistor electrodes for reading the information stored therein.
Great care is however to be adopted in controlling the read potentials applied to the memory cell storage elements; in fact, if these potentials are too high, a spurious injection of charges into the MOS transistor's charge retention element may take place, which alter the amount of charge in the charge retention element and thus the MOS transistor threshold voltage; this effect, usually referred to as “soft” programming, may cause an initially non-programmed memory cell storage element to become programmed. If this occurs, the data stored in the memory cell, and thus in the memory device as a whole, are corrupted.
In particular, in order to avoid or at least limit the risk of soft programming, it is necessary to carefully control the memory cell storage element drain potential: if the drain potential is not sufficiently low, the memory cell storage element is said to experience a drain stress, and this may induce the injection and/or tunneling of charges into the charge retention element.
The effect of drain stress on soft programming is particularly felt when the memory cell undergoes a large number of read accesses, and/or when the read potentials are applied to the memory cell for a relatively long time.
Conventionally, a biasing transistor is placed in series with the memory cell storage element, having the function of biasing the drain of the storage element. The biasing transistor, typically an N-channel MOSFET, is controlled by a biasing voltage which, typically, is generated by means of a voltage partition from an initially higher voltage, which can be the supply voltage (VDD) of the memory device integrated circuit, or an internally-generated voltage higher than the supply voltage, generated on-chip by a charge-pump voltage booster. The voltage partition is typically achieved using a resistive voltage partitioner made up of a certain number diode-connected P-channel and N-channel MOSFETs connected in series to each other (the specific number of these transistors depending on several parameters such as the initial voltage, the target biasing voltage, the MOSFETs' threshold voltage and so on).
One such solution, in addition to being rather power consuming (a crowbar current flows through the voltage partitioner), has a very limited precision and does not guarantee that the storage element biasing voltage is sufficiently stable, depending on process parameters such as the MOSFETs' threshold voltages, and there is no control on the voltage thus generated.
In particular, no control is operated on the threshold voltage of the biasing MOSFETs, which as known is subject to changes due to process statistical parameter variations and operating temperature.
This limited stability and predictability of the memory cell storage element biasing voltage, and thus of the drain voltage of the storage element, is very undesirable: if the drain voltage rises too much, soft-programming becomes significant, while too low a drain voltage may impair the operation of the sensing circuits that have to sense the current sunk by the storage element.